Luiz Alberto Crispiniano Garcia
November 11, 2025
Introduced BitwiseRAMLM — a per-bit output language model with only 16 clusters that outperforms the 50K-cluster tiered architecture. Plus plug-and-play gating that works across both architectures.
Major data model migration removing the Phase abstraction, plus deep work on tiered architecture with Metal GPU sparse forward and tier bits grid sweep.
Shipped a complete dashboard with charts and real-time updates, an iOS/iPadOS companion app, and the first gating experiments.
Built an experiments management system and a SvelteKit dashboard for real-time monitoring of optimization runs.
Built a structured optimization pipeline: coarse GA search narrows the space, fine TS search refines. Introduced fitness calculators for multi-objective optimization.
Discovered that asymmetric bit allocation across frequency tiers dramatically improves language model performance. Built overnight sweep infrastructure.
The most productive week yet. Built the complete RAM Transformer architecture, comprehensive benchmarks, and started the language model experiments.
Initial work on key-value memory mechanisms and laying the groundwork for the RAM Transformer architecture.
Improving the core architecture with PyTorch vectorization and cleaning up the foundation for what will become the RAM Transformer.
Describing the baseline of the baseline architecture, the repository and the first toy experiments with results.
Short description of what this project is about, goals, and the workflow you plan to follow.